2026.09장인호 학생 "IEEE Seoul Section 우수논문상 " 수상 (RF/아날로그 회로 워크샵)All news
Research

Research.

Data converters and mixed-signal circuits for communication, sensing, memory and computing.

Overview.

MCAS Lab at the University of Seoul designs mixed-signal integrated circuits: data converters, high-speed wireline and wireless interfaces, NAND flash memory circuits, and analog design automation, for communication, automotive, memory and AI systems.

01
ADC / DAC

Data converters

Mixed-signal integrated circuits connecting analog signals and digital systems.

Mixed-Signal Integrated Circuit Design — Data Converters
02
DESIGN AUTOMATION

Synthesizable analog

Analog circuits and ADCs with reusable, synthesizable building blocks.

Synthesizable Analog Circuit & Analog-to-Digital Converter (ADC)
03
LOW-POWER SENSING

Biomedical interfaces

Low-power SAR ADCs for biomedical monitoring and signal acquisition.

Low-power Successive-approximation-register (SAR) ADC for Bio-medical Monitoring System
04
HIGH-SPEED LINKS

High-speed conversion

Ultra-high-speed analog-to-digital conversion for next-generation communication systems.

Ultra-High-Speed A/D Conversion Systems for 5G & Future Communication System
05
EDGE COMPUTING

Mixed-mode intelligence

Energy-efficient mixed-mode DNN accelerators for edge-computing applications.

Energy-Efficient Mixed-mode Deep Neural Network (DNN) Accelerators for Edge-computing
Chip micrographs

Chips.

Chips designed and measured at MCAS Lab.

Die photo: 7-bit 32-GS/s time-interleaved SAR ADC
7-bit 32-GS/s time-interleaved SAR ADC28-nm CMOS
Die photo: 7-bit 3-GS/s two-step flash ADC with sample-and-hold sharing
7-bit 3-GS/s two-step flash ADC with sample-and-hold sharing40-nm CMOS · JSSC 2022
Die photo: 7-bit 32-GS/s SAR ADC with background channel-mismatch calibration
7-bit 32-GS/s SAR ADC with background channel-mismatch calibration40-nm CMOS · TCAS-II 2020
Die photo: 12-bit 200-MS/s single-amplifier dual-residue pipelined-SAR ADC
12-bit 200-MS/s single-amplifier dual-residue pipelined-SAR ADC40-nm CMOS · VLSI 2019
Die photo: 10-MHz-BW 74.4-dB-SNDR CT delta-sigma modulator with SAR-assisted noise coupling
10-MHz-BW 74.4-dB-SNDR CT delta-sigma modulator with SAR-assisted noise coupling28-nm CMOS · JSSC 2018
Die photo: 6-bit 20-GS/s time-interleaved DAC
6-bit 20-GS/s time-interleaved DAC65-nm CMOS · TCAS-II 2018
Die photo: Single-supply buffer-embedding SAR ADC with skip-reset chopping
Single-supply buffer-embedding SAR ADC with skip-reset chopping180-nm CMOS · JSSC 2020
Die photo: 18.5-nW 12-bit 1-kS/s reset-energy-saving SAR ADC
18.5-nW 12-bit 1-kS/s reset-energy-saving SAR ADC180-nm CMOS · TCAS-I 2018
Die photo: 0.6-V 12-bit 10-MS/s SATI-SAR ADC
0.6-V 12-bit 10-MS/s SATI-SAR ADC65-nm CMOS · JSSC 2016
Die photo: Code-based synthesizable 11-bit 50-MS/s SAR ADC
Code-based synthesizable 11-bit 50-MS/s SAR ADC28-nm CMOS · TCAS-II 2018
Die photo: Code-based synthesizable 12-bit 100-kS/s SAR ADC
Code-based synthesizable 12-bit 100-kS/s SAR ADC180-nm CMOS · TCAS-II 2018
Die photo: M-metric readout circuit for MLC phase-change memory
M-metric readout circuit for MLC phase-change memory65-nm CMOS · TCAS-II 2024
Die photo: Reference-free temperature-compensating PCM readout with flash-ADC sense amplifiers
Reference-free temperature-compensating PCM readout with flash-ADC sense amplifiers180-nm CMOS · JSSC 2019
Die photo: 0.08-to-680-MHz synthesizable MDLL with background phase-offset calibration
0.08-to-680-MHz synthesizable MDLL with background phase-offset calibration65-nm CMOS · TCAS-II 2018
Chip photograph collection: touch pen, 3D touch, sensor, biomedical and 5G wireless communication circuits
Select the image to view it at full size.
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