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6-bit 28GS/s High Speed DAC
To be submitted to IEEE Transactions on Instrumentation and Measurement (TIM).
Publications
Publications.
Journal articles, conference papers and manuscripts. * indicates the corresponding author.
In preparation.
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NAND Flash Memory Circuit Design
To be submitted to Advanced Science.
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Design Automation for NAND Flash Memory Circuits
To be submitted to the Design Automation Conference (DAC).
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Multi-Channel ADC for Physical AI
To be submitted to IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II).
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Uplink ADC for Software-Defined Vehicles
To be submitted to a conference.
29 publications
2026
A 0.2-mW 250-kHz-BW Fully Dynamic kT/C Noise-Shaping Discrete-Time Delta-Sigma Modulator with SAR-Assisted Input Feedforward and Digital Noise Coupling
Y.-H. Moon, K.-W. Park, Krishnakanth R, K. Kim, M. Kwon, M.-J. Seo*, and S.-T. Ryu*, IEEE J. Solid-State Circuits, accepted for publication, 2026.
2026
GRID: A Graph RL and gm/ID-Based Framework for Fast and Transferable Analog Circuit Optimization
Jiwon Seo, Jaeyoon Lee, Heejun Kang, and Min-Jae Seo*, Journal of Semiconductor Technology and Science (JSTS), vol. 26, no. 6, Dec. 2026 (early access).
2025
MoS2 Channel-Enhanced High-Density Charge Trap Flash Memory and Machine Learning-Assisted Sensing Methodologies for Memory-Centric Computing Systems
K.-H. Kim, J.-H. Park#, K.-J. Lee#, J.-W. Seo, Y.-K. Kim, J.-H. Choi, M.-J. Seo*, and B.-C. Jang*, Advanced Science 2501926 (2025)
2024
An M-metric Readout Circuit for MLC Phase Change Memory with a Comparator-Based Push-Pull Bit-Line Driver
J.-W. Kwon, D.-H. Jin, M.-J. Seo*, and S.-T. Ryu*, IEEE Trans. Circuits Syst. II Express Briefs, vol. 71, no. 11, pp. 4658-4662, Nov. 2024.
2024
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC
J.-H. Chung, Y.-D. Kim, C.-U. Park, K.-W. Park, D.-R. Oh, M.-J. Seo*, and S.-T. Ryu*, IEEE J. Solid-State Circuits, vol. 59, no. 8, pp. 2481–2491, Aug. 2024.
2023
Amorphous ITZO-Based Selector Device for Memristor Crossbar Array
K.-H. Kim, M.-J. Seo*, and B.-C. Jang, MDPI Micromachines, vol. 14, no. 3, Feb. 2023.
2022
A 7-bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique
D.-R. Oh, M.-J. Seo, and S.-T. Ryu, IEEE J. Solid-State Circuits, vol. 57, no. 9, pp. 2791-2801, Sept. 2022.
2021
A Single-Amplifier Dual-Residue Pipelined-SAR ADC
M.-J. Seo*, MDPI Electronics, vol. 10, no. 4, pp. 421, Feb. 2021.
2020
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability
(Invited), M.-J. Seo, D Jin, Y Kim, J Kim, and S.-T. Ryu, IEEE J. Solid-State Circuits, vol. 55, no. 10, pp. 2660–2669, Oct. 2020.
2020
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration
D.-S. Jo, B.-R.-S. Sung, M.-J. Seo, W.-C. Kim, and S.-T. Ryu, IEEE Trans. Circuits Syst. II Express Briefs, vol. 67, no. 4, pp. 610–614, Apr. 2020.
2019
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers
D.-H. Jin, J.-W. Kwon, M.-J. Seo, M.-Y. Kim, M.-C. Shin, S.-J. Kang, J.-H. Yoon, T.-S. Kim, and S.-T. Ryu, IEEE J. Solid-State Circuits, vol. 54, no. 6, pp. 1812–1823, Jun. 2019.
2018
A Reusable Code-based SAR ADC Design with CDAC Compiler and Synthesizable Analog Building Blocks
M.-J. Seo, Y.-J. Roh, D.-J. Chang, W. Kim, Y.-D. Kim, and S.-T. Ryu, IEEE Trans. Circuits Syst. II Express Briefs., vol. 65, no. 12, pp. 1904-1908, Dec. 2018.
2018
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-μm CMOS
M.-J. Seo, D.-H. Jin, Y.-D. Kim, S.-I. Hwang, J.-P. Kim, and S.-T. Ryu, IEEE Trans. Circuits Syst. I Regul. Pap., vol. 65, no. 11, pp. 3617-3627, Nov. 2018.
2018
A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC with Full-Binary Sub-DACs
S. N. Kim, W. C. Kim, M.-J. Seo, and S. T. Ryu, IEEE Trans. Circuits Syst. II Express Briefs, vol. 65, no. 9, pp. 1154–1158, Sep. 2018.
2018
A 4.2- mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling
I.-H. Jang, M.-J. Seo, S.-H. Cho, J.-K. Lee, S.-Y. Baek, S. Kwon, M. Choi, H.-J. Ko, and S.-T. Ryu, IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1139–1148, Apr. 2018.
2018
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration
D. Chang, M.-J. Seo, H. Hong, and S.-T. Ryu, IEEE Trans. Circuits Syst. II Express Briefs, vol. 65, no. 3, pp. 281–285, Mar. 2018
2018
A 2.7-M Pixels 64-mW CMOS Image Sensor with Multicolumn-Parallel Noise-Shaping SAR ADCs
S. I. Hwang, J. H. Chung, H. J. Kim, I. H. Jang, M.-J. Seo, S. H. Cho, H. Kang, M. Kwon, and S. T. Ryu, IEEE Trans. Electron Devices, vol. 65, no. 3, pp. 1119–1126, Mar. 2018.
2017
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC
D.-J. Chang, W. Kim, M.-J. Seo, H.-K. Hong, and S.-T. Ryu, IEEE Trans. Circuits Syst. I Regul. Pap., vol. 64, no. 2, pp. 322–332, Feb. 2017.
2016
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
W. Kim, H. Hong, Y. Roh, H. Kang, S. Hwang, D. Jo, D. Chang, M.-J. Seo, and S. Ryu, IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1826–1839, Aug. 2016.
2026
12mW 7.8 Gb/s NRZ/PAM-4 Dual-Mode Digital Spectrum Shaping Signaling Transmitter for Multidrop Interfaces in 28 nm CMOS
D. Kim, Y. Choi, S. Jang, E. Lee, K. Gharibdoust, A. Tajalli, F. Akbar, J. Chae, Min-Jae Seo, K. Lee, G. Kim, 2026 European Solid-State Electronics Research Conference (ESSERC), Sep. 2026.
2025
A 250kHz-BW 86.2dB-SNDR 176.7dB-FoMS Fully Dynamic kT/C Noise-Canceled DT DSM with SAR-Assisted Input FF and DNC
Young-Hun Moon, Kun-Woo Park, Kyunghoon Kim, Minho Kwon, Min-Jae Seo*, and Seung-Tak Ryu*, IEEE Asian Conference on Solid-State Circuits (ASSCC), Nov. 2025.
2025
A 184-dB-FoMS 25-kHz-BW 98.6-dB-SNDR Fully Dynamic Discrete-Time Delta-Sigma Modulator with Digital Noise Coupling
Young-Hun Moon, Kun-Woo Park, Kwan-Hoon Song, Kent Edrian Lozada, Min-Jae Seo*, and Seung-Tak Ryu*, IEEE International Midwest Symposium on Circuits and Systems, Aus. 2025.
2024
A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF
Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Chang-Un Park, Kun-Woo Park, Kwan-Hoon Song, Young-Hun Moon, Min-Jae Seo*, and Seung-Tak Ryu*, IEEE Symposium on VLSI Technology and Circuits, Jun. 2024.
2023
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC
J.-H. Chung, Y.-D. Kim, C.-U. Park, K.-W. Park, D.-R. Oh, M.-J. Seo*, and S.-T. Ryu*, IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023.
2020
A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section
J.P. Kim, W. Lee, J. Suh, H. Lee, K. Lee, H.Y. Ahn, M.-J. Seo, S.-T. Ryu, K. Aristovich, D. Holder, S.J. Kim, IEEE International Engineering in Medicine and Biology Conference (EMBC), Jul. 2020.
2019
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability
M.-J. Seo, D Jin, Y Kim, J Kim, D Chang, W Lim, J Chung, C Park, E Ahn and S.-T. Ryu, IEEE Asian Conference on Solid-State Circuits (ASSCC), Nov. 2019.
2019
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC
M.-J. Seo, Y.-D. Kim, J.-H. Chung, and S.-T. Ryu, IEEE Symposium on VLSI Circuits (VLSI-C), Jun. 2019.
2017
A 4.2mW 10MHz BW 74.4dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC
I.-H Jang, M.-J. Seo, M. Kim, J. Lee, S. Baek, S. Kwon, M. Choi, H. Ko, and S. Ryu, IEEE Symposium on VLSI Circuits (VLSI-C), Jun. 2017.
2015
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS
D.-R. Oh, J.-I. Kim, M.-J. Seo, J.-G. Kim, and S.-T. Ryu, IEEE European Solid-State Circuits Conference (ESSCIRC), Oct. 2015.
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Patents.
TRNG BASED ON AN OFFSET-TRACKING ADAPTIVE LEVEL SHIFTING INTERPOLATION ADC WITH LFSR-BASED POST-PROCESSING
Applied US Patent, 19/828,937, 2026.10.02
서민재, 김승현
타이밍 마진 확보 및 불필요한 위상 천이 차단이 가능한 아날로그 디지털 변환 장치
Applied KR Patent, 10-2026-0177112, 2026.09.16
서민재, 이재윤, 김형준, 김현우
공통 커패시터 배열을 공유하는 이중 변환 경로 기반의 축차근사형 아날로그 디지털 변환 장치 및 그 동작 방법
Applied KR Patent, 10-2026-0177122, 2026.09.16
서민재, 김형준, 이재윤, 김현우, 심동규
상보형 소스 팔로워 구조를 갖는 아날로그-디지털 변환기용 버퍼 및 이를 포함하는 아날로그-디지털 변환기
Applied KR Patent, 10-2026-0052047, 2026.03.23
서민재, 강희준, 정의훈, 전호진, 김홍진
오프셋 추종 적응형 레벨 시프팅 인터폴레이션 ADC를 이용한 진성 난수 발생기
Applied KR Patent, 10-2026-0022387, 2026.02.04
서민재, 심동규, 김승현
LFSR 기반 후처리를 포함하는 오프셋 추종 적응형 레벨 시프팅 인터폴레이션 ADC 기반 진성 난수 발생기
Applied KR Patent, 10-2026-0021411, 2026.02.03
서민재, 김승현
노이즈 보정 기반 회로 파라미터 최적화 시스템 및 방법
Applied KR Patent, 10-2025-0055385, 2025.04.28
서민재, 서지원
머신러닝 기반의 회로 시뮬레이션 엔진 대체 모델 학습 방법 및 이를 이용한 파라미터 최적화 방법
Applied KR Patent, 10-2025-0055389, 2025.04.28
서민재, 서지원
Multi-Hole 구조의 WL Cut 위치에 따른 WL Rs Skew 개선 방안
Applied KR Patent @ Samsung, P20210128950
Multi-Hole 구조에서 SSL Prepulse 시간단축을 위한 SSL Neg. Disch. Control 방법
Applied KR Patent @ Samsung, P20200144152
메모리회로에서 Word-line Leakage 전류 검출 방법
Applied KR Patent @ Samsung, P20190023386
ELECTRONIC CIRCUIT FOR IMPLEMENTING MODULATOR CONFIGURED TO PERFORM NOISE SHAPING IN DIGITAL DOMAINANALOG TO DIGITAL CONVERTER
Registered Taiwan Patent, I737916, 2021.09.01
류승탁, 장일훈, 서민재, 김미영, 이재근, 백승엽, 최병주, 고형종
ANALOG TO DIGITAL CONVERTER
Registered US Patent, 10,931,298, 2021.02.23
류승탁, 서민재, 김종팔
ELECTRONIC CIRCUIT INCLUDING PIPELINE CONVERTING CIRCUIT
Registered US Patent, 10,873,337, 2020.12.22
류승탁, 서민재
ANALOG-TO-DIGITAL CONVERTER (ADC) WITH RESET SKIPPING OPERATION AND ANALOG-TO-DIGITAL CONVERSION METHOD
Registered US Patent, 10,680,636, 2020.06.09
김종팔, 김예담, 류승탁, 서민재, 진동환
파이프라인 변환 회로를 포함하는 전자회로
Registered KR Patent, 10-2116669-0000, 2020.05.25.
류승탁, 서민재