We design mixed-signal integrated circuits that connect the analog world to digital systems: data converters, high-speed wireline and wireless interfaces, NAND flash memory circuits and analog design automation, for software-defined vehicles and physical AI.
MCAS Lab at the University of Seoul designs mixed-signal integrated circuits: data converters, high-speed wireline and wireless interfaces, NAND flash memory circuits, and analog design automation, for communication, automotive, memory and AI systems.
All researchMixed-signal integrated circuits connecting analog signals and digital systems.
Analog circuits and ADCs with reusable, synthesizable building blocks.
Low-power SAR ADCs for biomedical monitoring and signal acquisition.
Ultra-high-speed analog-to-digital conversion for next-generation communication systems.
Energy-efficient mixed-mode DNN accelerators for edge-computing applications.
7-bit 32-GS/s time-interleaved SAR ADC28-nm CMOS
7-bit 3-GS/s two-step flash ADC with sample-and-hold sharing40-nm CMOS · JSSC 2022
7-bit 32-GS/s SAR ADC with background channel-mismatch calibration40-nm CMOS · TCAS-II 2020
12-bit 200-MS/s single-amplifier dual-residue pipelined-SAR ADC40-nm CMOS · VLSI 2019
10-MHz-BW 74.4-dB-SNDR CT delta-sigma modulator with SAR-assisted noise coupling28-nm CMOS · JSSC 2018
6-bit 20-GS/s time-interleaved DAC65-nm CMOS · TCAS-II 2018
Single-supply buffer-embedding SAR ADC with skip-reset chopping180-nm CMOS · JSSC 2020
18.5-nW 12-bit 1-kS/s reset-energy-saving SAR ADC180-nm CMOS · TCAS-I 2018
0.6-V 12-bit 10-MS/s SATI-SAR ADC65-nm CMOS · JSSC 2016
Code-based synthesizable 11-bit 50-MS/s SAR ADC28-nm CMOS · TCAS-II 2018
Code-based synthesizable 12-bit 100-kS/s SAR ADC180-nm CMOS · TCAS-II 2018
M-metric readout circuit for MLC phase-change memory65-nm CMOS · TCAS-II 2024
Reference-free temperature-compensating PCM readout with flash-ADC sense amplifiers180-nm CMOS · JSSC 2019
0.08-to-680-MHz synthesizable MDLL with background phase-offset calibration65-nm CMOS · TCAS-II 2018Y.-H. Moon, K.-W. Park, Krishnakanth R, K. Kim, M. Kwon, M.-J. Seo*, and S.-T. Ryu*, IEEE J. Solid-State Circuits, accepted for publication, 2026.
J.-H. Chung, Y.-D. Kim, C.-U. Park, K.-W. Park, D.-R. Oh, M.-J. Seo*, and S.-T. Ryu*, IEEE J. Solid-State Circuits, vol. 59, no. 8, pp. 2481–2491, Aug. 2024.
M.-J. Seo, D.-H. Jin, Y.-D. Kim, S.-I. Hwang, J.-P. Kim, and S.-T. Ryu, IEEE Trans. Circuits Syst. I Regul. Pap., vol. 65, no. 11, pp. 3617-3627, Nov. 2018.
We are looking for graduate students interested in mixed-signal and data-converter circuit design. Please email Prof. Min-Jae Seo to talk about research topics and admission.
